1. |
Low Leakage Fully Half-Select-Free Robust SRAM Cells with BTI Reliability Analysis - 2018
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Abstract
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2. |
Fractional- Order Differentiators and Integrators with Reduced Circuit Complexity - 2018
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Abstract
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3. |
High speed and low power preset-able modified TSPC D flip-flop design and performance comparison with TSPC D flip-flop - 2018
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Abstract
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4. |
A High Performance Gated Voltage Level Translator with Integrated Multiplexer - 2018
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Abstract
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5. |
A Low-Power High-Speed Comparator for Precise Applications - 2018
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Abstract
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6. |
A Novel Five-input Multiple-function QCA Threshold Gate - 2018
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Abstract
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7. |
A Novel Design of Flip-Flop Circuits using Quantum Dot Cellular Automata (QCA) - 2018
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Abstract
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8. |
Binary To Gray Code Converter Implementation Using QCA - 2018
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Abstract
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9. |
MAES: Modified Advanced Encryption Standard for Resource Constraint Environments - 2018
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Abstract
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10. |
Low-power Implementation of Mitchell's Approximate Logarithmic Multiplication for Convolutional Neural Networks - 2018
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Abstract
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11. |
Chip Design for Turbo Encoder Module for In-Vehicle System - 2018
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Abstract
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12. |
The Design and Implementation of Multi – Precision Floating Point Arithmetic Unit Based on FPGA - 2018
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Abstract
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13. |
Unbiased Rounding for HUB Floating-point Addition - 2018
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Abstract
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14. |
Low-Complexity VLSI Design of Large Integer Multipliers for Fully Homomorphic Encryption - 2018
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Abstract
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15. |
FPGA Implementation of an Improved Watchdog Timer for Safety-critical Applications - 2018
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Abstract
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16. |
EEG Signal Denoising based on Wavelet Transform using Xilinx System Generator - 2018
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17. |
An Approach to LUT Based Multiplier for Short Word Length DSP Systems - 2018
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Abstract
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18. |
A Low Error Energy-Efficient Fixed-Width Booth Multiplier with Sign-Digit-Based Conditional Probability Estimation - 2018
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Abstract
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19. |
Tap Delay-and-Accumulate Cost Aware Coefficient Synthesis Algorithm for the Design of Area-Power Efficient FIR Filters - 2018
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Abstract
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20. |
FIR Filter Design Based On FPGA - 2018
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Abstract
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21. |
Area and Power Efficient VLSI Architecture of Distributed Arithmetic Based LMS Adaptive Filter - 2018
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Abstract
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22. |
Toward Energy-Efficient Stochastic Circuits Using Parallel Sobol Sequences - 2018
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Abstract
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23. |
Low-Power Approximate Multipliers Using Encoded Partial Products and Approximate Compressors - 2018
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Abstract
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24. |
Vector Processing-Aware Advanced Clock-Gating Techniques for Low-Power Fused Multiply-Add - 2018
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Abstract
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25. |
Design and simulation of CRC encoder and decoder using VHDL - 2018
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Abstract
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26. |
Reconfigurable Decoder for LDPC and Polar Codes - 2018
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Abstract
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27. |
Low-Power Noise-Immune Nano scale Circuit Design Using Coding-Based Partial MRF Method - 2018
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Abstract
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28. |
An Efficient VLSI Architecture for Convolution Based DWT Using MAC - 2018
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Abstract
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29. |
Basic-Set Trellis Min–Max Decoder Architecture for Non binary LDPC Codes With High-Order Galois Fields - 2018
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Abstract
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30. |
Double Error Cellular Automata-Based Error Correction with Skip-mode Compact Syndrome Coding for Resilient PUF Design - 2018
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Abstract
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31. |
Extending 3-bit Burst Error-Correction Codes With Quadruple Adjacent Error Correction - 2018
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Abstract
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32. |
Efficient Implementations of 4-Bit Burst Error Correction for Memories - 2018
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Abstract
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33. |
A Single and Adjacent Error Correction Code for Fast Decoding of Critical Bits - 2018
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Abstract
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34. |
Improving Error Correction Codes for Multiple-Cell Upsets in Space Applications - 2018
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Abstract
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35. |
Parallel Pseudo-Exhaustive Testing of Array Multipliers with Data-Controlled Segmentation - 2018
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Abstract
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36. |
Logic BIST with Capture-per-Clock Hybrid Test Points - 2018
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Abstract
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37. |
Flexible Architecture of Memory BISTs - 2018
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Abstract
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38. |
Automotive Functional Safety Assurance by POST with Sequential Observation - 2018
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Abstract
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39. |
A High Performance Scan Flip-Flop Design for Serial and Mixed Mode Scan Test - 2018
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Abstract
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40. |
VLSI design of low-cost and high-precision fixed-point reconfigurable FFT processors - 2018
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Abstract
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41. |
Low Power Area-Efficient DCT Implementation Based on Markov Random Field-Stochastic Logic - 2018
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Abstract
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42. |
An Area Efficient 1024-Point Low Power Radix-22 FFT Processor with Feed-Forward Multiple Delay Commutators - 2018
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Abstract
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43. |
An Efficient FPGA Implementation of HEVC Intra Prediction - 2018
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Abstract
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44. |
Architecture Generator for Type-3 Unum Posit Adder/Subtractor - 2018
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Abstract
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45. |
Efficient Design for Fixed-Width Adder-Tree - 2018
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Abstract
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46. |
Research and implementation of hardware algorithms for multiplying binary numbers - 2018
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Abstract
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47. |
A 32-bit 4×4 Bit-Slice RSFQ Matrix Multiplier - 2018
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Abstract
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48. |
Towards Efficient Modular Adders based on Reversible Circuits - 2018
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Abstract
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49. |
Systematic Design of an Approximate Adder: The Optimized Lower Part Constant-OR Adder - 2018
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Abstract
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50. |
Reducing the Hardware Complexity of a Parallel Prefix Adder - 2018
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Abstract
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