Low-Power Design for a Digit-Serial Polynomial Basis Finite Field Multiplier Using Factoring Technique - 2017 PROJECT TITLE :Low-Power Design for a Digit-Serial Polynomial Basis Finite Field Multiplier Using Factoring Technique - 2017ABSTRACT:In CMOS-based application-specific integrated circuit (ASIC) designs, total power consumption is dominated by dynamic power, where dynamic power consists of two major parts, particularly, switching power and internal power. In this paper, we present an occasional-power design for a digit-serial finite field multiplier in GF(a pair of m ). Within the proposed style, a factoring technique is employed to reduce switching power. To the best of our information, factoring methodology has not been reported in the literature being employed in the planning of a finite field multiplier at an architectural level. Logic gate substitution is also used to cut back internal power. Our proposed style along with several existing similar works have been realized for GF(2 233 ) on ASIC platform, and a comparison is made between them. The synthesis results show that the proposed multiplier design consumes a minimum of 27.8p.c lower total power than any previous work as compared. Did you like this research project? To get this research project Guidelines, Training and Code... Click Here facebook twitter google+ linkedin stumble pinterest Scenario-Aware Dynamic Power Reduction Using Bias Addition - 2017 Multiplier less Unity-Gain SDF-FFTS - 2017
