PROJECT TITLE :
A Dual-Clock VLSI Design of H.265 Sample Adaptive Offset Estimation for 8k Ultra-HD TV Encoding - 2017
Sample adaptive offset (SAO) is a newly introduced in-loop filtering component in H.265/High Potency Video Coding (HEVC). While SAO contributes to a notable coding efficiency improvement, the estimation of SAO parameters dominates the complexity of in-loop filtering in HEVC encoding. This paper presents an economical VLSI design for SAO estimation. Our style options a twin-clock design that processes statistics assortment (SC) and parameter call (PD), the 2 main purposeful blocks of SAO estimation, at high- and low-speed clocks, respectively. Such a technique reduces the general space by fifty sixp.c by addressing the heterogeneous data flows of SC and PD. To further improve the area and power efficiency, algorithm-architecture co-optimizations are applied, together with a coarse vary choice (CRS) and an accumulator bit width reduction (ABR). CRS shrinks the range of fine processed bands for the band offset estimation. ABR additional reduces the world by narrowing the accumulators of SC. They together achieve another 25p.c area reduction. The proposed VLSI design is capable of processing 8k at a hundred and twenty-frames/s encoding. It occupies 51k logic gates, solely one-third of the circuit area of the state-of-the-art implementations.
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