PROJECT TITLE :
Low-Power Addition with Borrow-Save Adders under Threshold Voltage Variability - 2018
It is well-known that reduced logic depth permits for operation at low voltages, therefore reducing power dissipation. But, such circuits are particularly susceptible to variations, that may compromise expected benefits. This transient presents a resolution for low-power addition below variability, that successfully handles the challenge of increased threshold voltage variation. Specifically, we tend to quantitatively compare the impact of variation on the performance of ripple-carry adder (RCA) and borrow-save adder (BSA), quantify the average power reduction achieved by BSA attained at low voltage values, at the price of increased delay variation, and propose a technique that enhances BSA tolerance to variations. Using statistical timing evaluation at the 45-nm and thirty two-nm nodes, we tend to estimate the most critical path delay variation and average power dissipation of BSA at completely different supply voltages. Our analysis reveals that BSA achieves three times smaller customary deviation of maximum delay than RCA at the same provide voltage. Also, we show that it is possible to substantially scale back the provision voltage, decreasing by virtually 60% the power dissipation of BSA in comparison to a counterpart operating at nominal voltage while keeping most delay less than that of RCA. Furthermore, straightforward style optimizations in the look of BSA are introduced that trade latency for variability, significantly reducing normalized standard deviation of the maximum delay.
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