PROJECT TITLE :
Sense-Amplifier-Based Flip-Flop With Transition Completion Detection for Low-Voltage Operation - 2018
A novel high-speed and highly reliable sense-amplifier-primarily based flip-flop with transition completion detection (SAFF-TCD) is proposed for low supply voltage (VDD) operation. The SAFF-TCD adopts the internally generated detection signal to point the completion of sense-amplifier stage transition. The detection signal gates the pull-down path of the sense-amplifier stage and the slave latch, thus overcoming the operational yield degradation, current rivalry, and glitches of previous SAFFs. The operational yield, speed, hold time, energy consumption, and area of the proposed and former FFs are quantitatively compared for a wide selection of VDD with twenty two-nm FinFET technology. It is shown that the minimum VDD of the SAFF-TCD is 573 mV below that of previous SAFFs, that means the SAFF-TCD can operate even when VDD is during the close to-threshold or subthreshold region. At zero.3-zero.four V, the SAFF-TCD operates twice as fast as the master-slave-based mostly FF (MSFF) with a practical hold time. Even with these benefits, the energy consumption overhead is limited to less than twentyp.c compared with that of MSFF, and the world is kind of like that of previous SAFFs.
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