An Efficient VLSI Architecture for Convolution Based DWT Using MAC - 2018


The fashionable real time applications related to Image Processing and etc., demand high performance discrete wavelet rework (DWT). This paper proposes the floating point multiply accumulate circuit (MAC) based mostly 1D/2D-DWT, where the MAC is used to find the outputs of high/low pass FIR filters. The proposed technique is implemented with forty five nm CMOS technology and the results are compared with various existing techniques. The proposed 8 x eight-point floating purpose 2-levels 2D-DWT achieves 27.half-dozenpercent and 83.7percent of reduction in total space and web power respectively as compared with existing DWT [nine].

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