PROJECT TITLE :
Adaptive Approximation in Arithmetic Circuits: A Low-Power Unsigned Divider Design - 2018
Many approximate arithmetic circuits have been proposed for top-performance and low-power applications. But, most styles are either hardware-economical with a low accuracy or terribly correct with a restricted hardware saving, mostly due to the use of a static approximation. In this paper, an adaptive approximation approach is proposed for the look of a divider. In this style, division is computed by employing a reduced-width divider and a shifter by adaptively pruning the input bits. Specifically, for a 2n/n division 2k/k bits are selected beginning from the foremost vital 'one' within the dividend/divisor. At the identical time, redundant least significant bits (LSBs) are truncated or if the amount of remaining LSBs is smaller than 2k for the dividend or k for the divisor, '0's are appended to the LSBs of the input. To avoid overflow, a two(k + one)/(k + one) divider is employed to compute the division of the 2k-bit dividend and therefore the k-bit divisor, each with the most vital bits being 'zero'. So, k <; n could be a key variable that determines the dimensions of the divider and therefore the accuracy of the approximate style. Finally, a slip-up correction circuit is proposed to recover the error caused by the shifter by using OR gates. The synthesis results in an industrial 28nm CMOS process show that the proposed sixteen/8 approximate divider using an eight/four correct divider is a pair of.5? as quick and consumes 34.forty twop.c of the facility of the correct 16/8 style. Compared with the other approximate dividers, the proposed design is considerably additional accurate at an identical power-delay product. Moreover, simulation results show that the proposed approximate divider outperforms the other styles in 2 image processing applications.
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