Low-Complexity VLSI Design of Large Integer Multipliers for Fully Homomorphic Encryption - 2018


Giant integer multiplication has been widely employed in fully homomorphic encryption (FHE). Implementing possible large integer multiplication hardware is so essential for accelerating the FHE evaluation method. During this paper, a unique and efficient operand reduction theme is proposed to scale back the area demand of radix-r butterfly units. We tend to additionally extend the only-port, merged-bank memory structure to the design of range theoretic rework (NTT) and inverse NTT (INTT) for any space minimization. Also, an economical memory addressing theme is developed to support both NTT/INTT and resolving carries computations. Experimental results reveal that vital space reductions will be achieved for the targeted 786432- and 1179648-bit NTT-primarily based multipliers designed using the proposed schemes in comparison with the related works. Moreover, the 2 multiplications will be accomplished in zero.196 and a couple of.twenty one ms, respectively, based on 90-nm CMOS technology. The low-complexity feature of the proposed giant integer multiplier styles is so obtained while not sacrificing the time performance.

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