Low Leakage Fully Half-Select-Free Robust SRAM Cells with BTI Reliability Analysis - 2018

PROJECT TITLE :

Low Leakage Fully Half-Select-Free Robust SRAM Cells with BTI Reliability Analysis - 2018

ABSTRACT:

This paper presents two totally different topologies of 11T SRAM cells with absolutely 0.5-select-free strong operation for bit-interleaving implementation. The proposed 11T-1 and 11T-a pair of cells successfully eliminate Scan disturb and Write 0.5-select disturb and also improve the Write-ability by using power-cutoff and write “zero”/ “1” solely techniques. The 11T-1 and 11T-a pair of cells achieve one.eighty three× and one.7× higher write-yield whereas both achieve approximately 2× higher read-yield as compared with 6T cell (at V DD =0.nine V). The proposed 11T-1 cell conjointly shows 13.six% higher mean Write-margin (WM) compared with existing 11T cell. Each the proposed cells successfully eliminate floating node condition encountered in earlier power cut-off cells throughout write half-select. Monte-Carlo simulation confirms low-voltage operation without any extra peripheral assist circuits. We tend to additionally gift a comparative analysis of Bias Temperature Instability reliability impacting the SRAM performance in a very predictive 32nm high-k metal gate CMOS technology. Beneath static stress, the Browse Static Noise Margin (RSNM) reduces for all cells. However, 11T-1 and 11T-two cells improve RSNM by a pair of.seven% and three.3p.c beneath relaxed stress of ten/ninety. Moreover, the proposed 11T-1 (11T-2) cell improves WM by 7.twop.c (13.a pair ofp.c), reduces write power by twenty eight.zero% (twenty.4%) and leakage power by 85.sevenp.c (86.ninepercent), degrades write delay by thirty eight.onepercent (twenty three.threep.c) while not affecting read delay/power over a amount of 108 seconds (approx. three years). The 11T-one (11T-two) cell exhibits 4.eight% higher (a pair ofpercent lower) space overhead as compared to earlier 11T cell. Hence, the proposed 11T cells are an excellent choice for reliable SRAM design at nanoscale amidst method variations and transistor aging impact and will additionally be used in bit-interleaving design to realize multi-cell upset immunity.

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