Design and Evaluation of Approximate Logarithmic Multipliers for Low Power Error-Tolerant Applications - 2018


In this paper, the designs of both non-iterative and iterative approximate logarithmic multipliers (ALMs) are studied to further scale back power consumption and improve performance. Non-iterative ALMs, that use 3 inexact mantissa adders, are presented. The proposed iterative ALMs (IALMs) use a collection-one adder in each mantissa adders throughout an iteration; they conjointly use lower-part-or adders and approximate mirror adders for the final addition. Error analysis and simulation results are also provided; it's found that the proposed approximate LMs with an acceptable variety of inexact bits achieve higher accuracy and lower power consumption than conventional LMs using actual units. Compared with standard LMs with precise units, the normalized mean error distance of 16-bit approximate LMs is decreased by up to eighteenp.c and the ability-delay product incorporates a reduction of up to thirty seven%. The proposed approximate LMs are also compared with previous approximate multipliers; it's found that the proposed approximate LMs are best suitable for applications allowing larger errors, however requiring lower energy consumption. Approximate Booth multipliers work applications with less stringent power necessities, but conjointly requiring smaller errors. Case studies for error-tolerant computing applications are provided.

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