Design of Efficient Programmable Test-per-Scan Logic BIST Modules - 2017


This paper focus on the design of Programmable Logic BIST structures for Very Large Scale Integration (VLSI) Integrated Circuit(IC) testing. The advancements happening in VLSI technology daily have created chip testing a lot of complicated. This has paved approach for the increased popularity of Logic Engineered In Self Check (LBIST) compared to Automatic Take a look at Equipment (ATE). Logic BIST permits self testing of chips with the assistance of an extra designed-in hardware structure inside the circuit. Check-per-scan Logic BIST structure includes Check pattern generator, Response Analyzer, ROM, and Comparator. LFSR will the role of take a look at pattern generator in Logic BIST since it is a lot of efficient than binary counters. MISR is commonly used as an output response analyzer which acts as another to n-parallel LFSRs. Comparator compares the responses stored in ROM and MISR output. Reconfigurability is added to each structural element in BIST to enhance the fault coverage of IC testing. The proposed structural design is simulated in Modelsim RTL simulator. The different sized (sixteen, 32, forty eight) programmable structures in Logic BIST were synthesized in Xilinx Spartan 3E and Spartan six for implementing them on FPGA. Four structural representations like Modular, Standard, Hybrid and Complete kind were implemented for PRPG and MISR design. All the styles were synthesized in ASIC in RTL compiler using 90nm standard cell technology library. The results of the proposed programmable PRPG and MISR designs were analyzed for speed, power and area with the equivalent modules generated by third party sign-off tool.

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