Reducing the Hardware Complexity of a Parallel Prefix Adder - 2018


Currently, parallel prefix adders (PPA) are thought of effective combinational circuits for performing the binary addition of two multi-bit numbers. These adders are widely utilized in arithmetic-logic units, that are elements of recent processors, like microprocessors, digital signal processors, etc. This paper deals with Kogge-Stone adder, that is one amongst the fastest PPA. When performing the schematic implementation, this adder incorporates a massive hardware complexity. So, during this work for reducing its hardware complexity the scheme of modified PPA has been developed. The performance parameters thought of for the comparative analysis of the presented adders are: the number of logic gates, Quine-complexity and most delay obtained when schematic modeling in CAD surroundings Quartus II based mostly on FPGA Altera EP2C15AF484C6. As a result, when simulation of thirty two-bit adder, Kogge-Stone adder and changed PPA have similar most delay. But changed PPA has reduced hardware complexity by 22.5percent compared to Kogge-Stone adder.

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