Reliable Low-Latency Viterbi Algorithm Architectures Benchmarked on ASIC and FPGA - 2017


The Viterbi algorithm is usually applied to a number of sensitive usage models together with decoding convolutional codes employed in communications like satellite communication, cellular relay, and wireless native area networks. Moreover, the algorithm has been applied to automatic speech recognition and storage devices. In this paper, efficient error detection schemes for architectures based mostly on low-latency, low-complexity Viterbi decoders are presented. The advantage of the proposed schemes is that reliability necessities, overhead tolerance, and performance degradation limits are embedded in the structures and will be custom-made accordingly. We have a tendency to also gift 3 variants of recomputing with encoded operands and its modifications to detect both transient and permanent faults, as well as signature-based schemes. The instrumented decoder architecture has been subjected to intensive error detection assessments through simulations, and application-specific integrated circuit (ASIC) [thirty two nm library] and field-programmable gate array (FPGA) [Xilinx Virtex-six family] implementations for benchmark. The proposed fine-grained approaches can be utilized primarily based on reliability objectives and performance/implementation metrics degradation tolerance.

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