PROJECT TITLE :
A Simple Yet Efficient Accuracy- Configurable Adder Design - 2018
Approximate computing may be a promising approach for low-power IC design and has recently received considerable analysis attention. To accommodate dynamic levels of approximation, a few accuracy-configurable adder (ACA) styles are developed in the past. But, these styles tend to incur giant area overheads as they depend upon either redundant computing or difficult carry prediction. Some of these designs embrace error detection and correction circuitry, which more increase the realm. In this paper, we tend to investigate a simple ACA style that contains no redundancy or error detection/correction circuitry and uses very straightforward carry prediction. The simulation results show that our style dominates the newest previous work on accuracy-delay-power tradeoff whereas using 39percent lower space. In the simplest case, the iso-delay power of our style is only 16% of correct adder irrespective of degradation in accuracy. One variant of this design provides finer-grained and bigger tunability than that of the previous works. Moreover, we tend to propose a delay-adaptive self-configuration technique to any improve the accuracy-delay-power tradeoff. The blessings of our technique are confirmed by the applications in multiplication and discrete cosine transform computing.
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