A Single and Adjacent Error Correction Code for Fast Decoding of Critical Bits - 2018


Several systems have essential bits which should be decoded at high speeds; for instance, flags to mark the start and end of a packet (SOP and EOP) verify subsequent actions, so they have to be decoded initial and quick. This paper presents a new single and adjacent error correction (SAEC) code; as the codewords have crucial bits, the proposed code accomplishes a fast decoding for them. The proposed code could be a systematic code and permits shortening. This is accomplished by reducing the information bits, therefore that columns within the H matrix can be eliminated, whereas still keeping both the SAEC capability and the systematic feature, except for an odd variety of knowledge bits, an adjustment step in essential bits is needed. It is shown that the check bit length of the proposed code is nearly the identical as that of the ancient (optimal) Hamming SAEC code. The decoder of the proposed SAEC code is compared with the ancient Hamming SAEC code; this comparison shows that on average, the delay time for the vital bits is reduced by 6 percent compared with the ancient Hamming SAEC code (thus at the identical reduction level as a previous SEC scheme for fast decoding of important bits over a traditional SEC code). Conjointly, the realm and power consumption of the proposed decoder show average reductions of 12 percent and ten p.c compared with the decoder of a traditional SAEC code.

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