Research and implementation of hardware algorithms for multiplying binary numbers - 2018


The structures of matrix and tree-like multipliers of binary numbers were reviewed and their system characteristics were determined. The internal structure of incomplete one-bit adder and pyramidal adder has been proposed, that allowed reducing the amount of kit within the investigated multiplier structures at times and increasing the speed by 1.8 times. Realization of these multipliers and their synthesis was made on FPGA of Xilinx Company. A comparative analysis of the obtained results was made, which created it potential for a designer to settle on the optimal structure of the multiplier to accomplish the task of hardware multiplying of binary numbers with given system characteristics.

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