PROJECT TITLE :
A High Performance Gated Voltage Level Translator with Integrated Multiplexer - 2018
Multiple offer voltages are commonly employed in designs to enable higher power performance through dedicated management of the supply voltage of the numerous useful units. In multiple supply voltage designs, circuits are partitioned into voltage islands that operate at their optimum provide voltages that necessitates the use of voltage level translators between them. This paper presents a high performance voltage level translator style aimed at minimizing insertion penalty by minimizing logic contention and thereby improving latency. Furthermore, the proposed voltage level translator design has an integrated logic multiplexer function built in through an enable signal. Simulation results of the proposed voltage level translator as compared with the standard voltage level translator shows upto forty two% delay reduction, combined with a power benefit upto 15p.c, for offer voltage starting from close to-threshold to higher than-threshold levels.
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