PROJECT TITLE :
Novel High speed Vedic Multiplier proposal incorporating Adder based on Quaternary Signed Digit number system - 2018
This paper presents a high-speed Vedic multiplier based mostly on the Urdhva Tiryagbhyam sutra of Vedic mathematics that includes a unique adder primarily based on Quaternary Signed digit variety system. 3 operations are inherent in multiplication: partial merchandise generation, partial products reduction and addition. A fast adder architecture therefore greatly enhances the speed of the general process. A Quaternary logic adder design is proposed that works on a hybrid of binary and quaternary number systems. A given binary string is first divided into quaternary digits of 2 bits every followed by parallel addition reducing the carry propagation delay. The design does not require a radix conversion module because the sum is directly generated in binary using the novel concept of an adjusting bit. The proposed multiplier design is compared with a Vedic multiplier based on multi voltage or multi price logic [MVL], Vedic Multiplier that includes a QSD adder with a conversion module for quaternary to binary conversion, Vedic multiplier that uses Carry Select Adder and a commonly used fast multiplication mechanism like Booth multiplier. All these styles are developed using Verilog HDL and synthesized by Synopsys Style Compiler. They need been realized using the open supply NAN gate 15nm technology library. The proposal shows a most of 88.seventy five% speed improvement with respect to Multi Price logic based 128×128 Vedic multiplier whereas the minimum is seventeen.47p.c.
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