Low-Power and Fast Full Adder by Exploring New XOR and XNOR Gates - 2018


In this paper, novel circuits for XOR/XNOR and simultaneous XOR-XNOR functions are proposed. The proposed circuits are highly optimized in terms of the power consumption and delay, which are due to low output capacitance and low short-circuit power dissipation. We have a tendency to additionally propose six new hybrid 1-bit full-adder (FA) circuits based on the novel full-swing XOR-XNOR or XOR/XNOR gates. Every of the proposed circuits has its own merits in terms of speed, power consumption, power-delay product (PDP), driving ability, and therefore on. To research the performance of the proposed styles, in depth HSPICE and Cadence Virtuoso simulations are performed. The simulation results, primarily based on the 65-nm CMOS process technology model, indicate that the proposed styles have superior speed and power against different FA styles. A new transistor sizing technique is presented to optimize the PDP of the circuits. Within the proposed method, the numerical computation particle swarm optimization algorithm is used to realize the required value for optimum PDP with fewer iterations. The proposed circuits are investigated in terms of variations of the supply and threshold voltages, output capacitance, input noise immunity, and the dimensions of transistors.

Did you like this research project?

To get this research project Guidelines, Training and Code... Click Here

PROJECT TITLE :Dynamically Updatable Ternary Segmented Aging Bloom Filter for OpenFlow-Compliant Low-Power Packet Processing - 2018ABSTRACT:OpenFlow, the most protocol for software-outlined networking, requires large-sized rule
PROJECT TITLE :A Low-Power High-Speed Comparator for Precise Applications - 2018ABSTRACT:A coffee-power comparator is presented. pMOS transistors are used at the input of the preamplifier of the comparator furthermore as the latch
PROJECT TITLE :Low-power Implementation of Mitchell's Approximate Logarithmic Multiplication for Convolutional Neural Networks - 2018ABSTRACT:This paper proposes an occasional-power implementation of the approximate logarithmic
PROJECT TITLE :Low-Power Approximate Multipliers Using Encoded Partial Products and Approximate Compressors - 2018ABSTRACT:Approximate computing has been thought of to boost the accuracy-performance tradeoff in error-tolerant
PROJECT TITLE :Vector Processing-Aware Advanced Clock-Gating Techniques for Low-Power Fused Multiply-Add - 2018ABSTRACT:The need for power potency is driving a rethink of style selections in processor architectures. Whereas vector

Ready to Complete Your Academic MTech Project Work In Affordable Price ?

Project Enquiry