PROJECT TITLE :
Low-Power and Fast Full Adder by Exploring New XOR and XNOR Gates - 2018
In this paper, novel circuits for XOR/XNOR and simultaneous XOR-XNOR functions are proposed. The proposed circuits are highly optimized in terms of the power consumption and delay, which are due to low output capacitance and low short-circuit power dissipation. We have a tendency to additionally propose six new hybrid 1-bit full-adder (FA) circuits based on the novel full-swing XOR-XNOR or XOR/XNOR gates. Every of the proposed circuits has its own merits in terms of speed, power consumption, power-delay product (PDP), driving ability, and therefore on. To research the performance of the proposed styles, in depth HSPICE and Cadence Virtuoso simulations are performed. The simulation results, primarily based on the 65-nm CMOS process technology model, indicate that the proposed styles have superior speed and power against different FA styles. A new transistor sizing technique is presented to optimize the PDP of the circuits. Within the proposed method, the numerical computation particle swarm optimization algorithm is used to realize the required value for optimum PDP with fewer iterations. The proposed circuits are investigated in terms of variations of the supply and threshold voltages, output capacitance, input noise immunity, and the dimensions of transistors.
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