A Low Error Energy-Efficient Fixed-Width Booth Multiplier with Sign-Digit-Based Conditional Probability Estimation - 2018 PROJECT TITLE :A Low Error Energy-Efficient Fixed-Width Booth Multiplier with Sign-Digit-Based Conditional Probability Estimation - 2018ABSTRACT:Fixed-width multipliers are intensively used in many DSP applications whose accuracy and energy efficiency affect the whole digital system to a massive extent. To enhance the computation accuracy, a Booth-encoded sign-digit-based mostly conditional likelihood estimation approach is proposed. A symmetric error distribution is obtained by taking the sign bit of the Booth-encoded multiplier into consideration when applying the conditional likelihood. Additionally, a more generalized mux-based estimation methodology is formulated for the circuit implementation, which reduces the delay time and power dissipation. Simulation results show that the proposed multiplier exhibits the most effective computation accuracy with the smallest amount energy per operation. It performs even higher for those operand lengths that aren't multiples of 4. The maximum reduction on energy-delay-error product will reach fourteen.8% compared with all its contenders among various operand lengths. Did you like this research project? To get this research project Guidelines, Training and Code... Click Here facebook twitter google+ linkedin stumble pinterest An Approach to LUT Based Multiplier for Short Word Length DSP Systems - 2018 Tap Delay-and-Accumulate Cost Aware Coefficient Synthesis Algorithm for the Design of Area-Power Efficient FIR Filters - 2018
