PROJECT TITLE :
An Approach to LUT Based Multiplier for Short Word Length DSP Systems - 2018
Short Word Length (SWL) DSP systems provide sensible performance as they method less knowledge-usually up to a few bits. Short Word Length systems could be designed using the FPGAs. FPGAs come back with several designed-in primitives like Look-up tables, Flip-flops, additional Carry logic, Memories and DSP components. All these primitives offer various approaches for FPGA based system design. This paper presents a way to use the Look-up tables to style three bit (three×3) constant coefficient unsigned integral multiplier for Short Word Length DSP systems. Besides, the feasibility of using Block ram and DSP components for Short Word Length DSP system (multiplier) is also administered as an alternate implementation approach. Result suggests the proposed method be the better one compared with other two implementations.
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