An Area Efficient 1024-Point Low Power Radix-22 FFT Processor with Feed-Forward Multiple Delay Commutators - 2018 PROJECT TITLE :An Area Efficient 1024-Point Low Power Radix-22 FFT Processor with Feed-Forward Multiple Delay Commutators - 2018ABSTRACT:Radix-a pair of k delay feed-back and radix-K delay commutator are the foremost well-known pipeline design for FFT style. This paper proposes a novel radix-two 2 multiple delay commutator design utilizing the advantages of the radix-two 2 algorithm, like simple butterflies and less memory demand. Therefore, it is more hardware efficient when implementing parallelism for higher throughput using multiple delay commutators or feed-forward data methods. Here, we tend to propose an improved input scheduling algorithm primarily based upon memory to eliminate energy required to shift data along the delay lines. A 1024-purpose FFT processor with 2 parallel knowledge paths is implemented in 65-nm CMOS method technology. The FFT processor occupies an space of three.six mm 2 , successfully operates in the provision voltage range from 0.four-one V and the most clock frequency of 600 MHz. For low voltage, high performance applications, the processor is in a position to control at four hundred MHz and consumes sixty.three mW or 77.2 nJ/FFT generating 800 Msamples/s at zero.6 V provide. Did you like this research project? To get this research project Guidelines, Training and Code... Click Here facebook twitter google+ linkedin stumble pinterest VLSI DSP Applications MTech Projects Low Power Area-Efficient DCT Implementation Based on Markov Random Field-Stochastic Logic - 2018 An Efficient FPGA Implementation of HEVC Intra Prediction - 2018
