An Efficient FPGA Implementation of HEVC Intra Prediction - 2018


Intra prediction algorithm used in High Potency Video Coding (HEVC) normal has terribly high computational complexity. In this paper, an efficient FPGA implementation of HEVC intra prediction is proposed for 4×4, 8×eight, 16×16 and 32×32 angular prediction modes. In the proposed FPGA implementation, one intra angular prediction equation is implemented using one DSP block in FPGA. The proposed FPGA implementation, within the worst case, will method fifty five Full HD (1920×1080) video frames per second. It's up to 34.66% less energy consumption than the first FPGA implementation of HEVC intra prediction. So, it will be used in portable shopper electronics products that need a true-time HEVC encoder.

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