Performance Analysis of a Low-Power High-Speed Hybrid 1-bit Full Adder Circuit - 2017


In this paper, a hybrid one-bit full adder design using both complementary metal-oxide-semiconductor (CMOS) logic and transmission gate logic is reported. The design was first implemented for one bit and then extended for thirty two bit conjointly. The circuit was implemented using Cadence Virtuoso tools in a hundred and eighty-and 90-nm technology. Performance parameters like power, delay, and layout area were compared with the existing designs like complementary pass-transistor logic, transmission gate adder, transmission function adder, hybrid pass-logic with static CMOS output drive full adder, and therefore on. For one.eight-V supply at 180-nm technology, the average power consumption (4.1563 µW) was found to be extraordinarily low with moderately low delay (224 ps) ensuing from the deliberate incorporation of terribly weak CMOS inverters as well as strong transmission gates. Corresponding values of the same were one.17664 µW and 91.3 ps at ninety-nm technology operating at 1.2-V offer voltage. The look was more extended for implementing thirty two-bit full adder additionally, and was found to be operating efficiently with only five.578-ns (two.forty five-ns) delay and 112.79-µW (53.thirty six-µW) power at a hundred and eighty-nm (ninety-nm) technology for one.eight-V (one.two-V) offer voltage. As compared with the present full adder designs, this implementation was found to offer vital improvement in terms of power and speed.

Did you like this research project?

To get this research project Guidelines, Training and Code... Click Here

PROJECT TITLE : Performance Analysis and Optimization of Cache-Assisted CoMP for Clustered D2D Networks ABSTRACT: Two promising strategies for supporting massive content delivery over wireless networks while mitigating the effects
PROJECT TITLE : Predictive Auto-scaling of Multi-tier Applications Using Performance Varying Cloud Resources ABSTRACT: The performance of the same kind of cloud resources, such as virtual machines (VMs), can change over time for
PROJECT TITLE : The Effects of Vehicle-to-Infrastructure Communication Reliability on Performance of Signalized Intersection Traffic Control ABSTRACT: Communications between vehicles and roadside infrastructure can give an
PROJECT TITLE : Short Text Topic Modeling Techniques, Applications, and Performance: A Survey ABSTRACT: The semantic understanding of short texts is required for a wide variety of real-world applications, so their analysis allows
PROJECT TITLE : Performance Improvement of a Parsimonious Learning Machine Using Metaheuristic Approaches ABSTRACT: When dealing with data stream mining, autonomous learning algorithms operate in an online fashion. This is desirable

Ready to Complete Your Academic MTech Project Work In Affordable Price ?

Project Enquiry