PROJECT TITLE :
Design Considerations for Energy-Efficient and Variation-Tolerant Nonvolatile Logic - 2018
Systems powered by harvested energy must consume terribly low power and stand up to frequent interruptions in power. Nonvolatile logic (NVL) addresses the latter by saving the system state in flipflops enhanced with spin-transfer torque magnetic tunnel junctions (STT-MTJs) as the nonvolatile storage devices. Manufacturing variations in the STT-MTJs and in CMOS transistors considerably cut back yield, resulting in overdesign and high-energy consumption. A detailed analysis of the planning tradeoffs in the driver circuitry for performing backup and restore, and a unique technique to style the energy optimal driver for a given yield is presented. Next, efficient designs of two nonvolatile flip-flop (NVFF) circuits are presented, in which the backup time is decided on a per-chip basis, ensuing in minimizing the energy wastage and satisfying the yield constraint. To attain a yield of 98p.c, the traditional approach would have to expend nearly 5x more energy than the minimum needed, whereas the proposed tunable approach expends solely 26% a lot of energy than the minimum. Additionally included are the energy consumption of the proposed NVFF designs when used in two larger function blocks. Experimental results were primarily based on a business forty-nm process design kit, and HSPICE simulations with foundry equipped statistical models and information.
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