Low Power Area-Efficient DCT Implementation Based on Markov Random Field-Stochastic Logic - 2018 PROJECT TITLE :Low Power Area-Efficient DCT Implementation Based on Markov Random Field-Stochastic Logic - 2018ABSTRACT:Markov Random Field (MRF) has been adopted to achieve high noise immunity for computing systems in deep sub-micron condition. However, complete MRF designs consume massive area overhead, limiting its direct hardware implementation for one-dimensional discrete cosine remodel. As a low-cost range representation, stochastic logic can efficiently simplify computing circuits. By combining the 2 techniques, we present an MRF-based mostly gate cluster design in order to attain area and power saving with high noise immunity for stochastic adders utilized in discrete cosine rework. To validate the performance of our style, we have a tendency to implement an eight-purpose one-dimensional discrete cosine remodel (1D-DCT) system applied the proposed design in sixty five nm CMOS technology. Simulation results show that the proposed design will achieve 7p.c higher noise-immunity with thirty onepercent space-saving for stochastic adders and fifty two% power-saving, compared with the realm-saving Master-and-slave stochastic 1D-DCT. The proposed design benefits outside sensors and biological moveable devices handling image compression. Did you like this research project? To get this research project Guidelines, Training and Code... Click Here facebook twitter google+ linkedin stumble pinterest VLSI DSP Applications MTech Projects VLSI design of low-cost and high-precision fixed-point reconfigurable FFT processors - 2018 An Area Efficient 1024-Point Low Power Radix-22 FFT Processor with Feed-Forward Multiple Delay Commutators - 2018
