A High Performance Scan Flip-Flop Design for Serial and Mixed Mode Scan Test - 2018


Over the years, serial scan design has become the de-facto design for testability technique. The simple testing and high test coverage has created it gain widespread industrial acceptance. However, there are penalties associated with the serial scan design. These penalties embody performance degradation, check knowledge volume, take a look at application time, and take a look at power dissipation. The performance overhead of scan design is because of the scan multiplexers added to the inputs of each flip-flop. In these days's very high-speed designs with minimum doable combinational depth, the performance degradation caused by the scan multiplexer has become magnified. Hence, to take care of circuit performance, the timing overhead of scan style must be addressed. In this paper, we have a tendency to propose a replacement scan flip-flop design that eliminates the performance overhead of serial scan. The proposed design removes the scan multiplexer from the useful path. The proposed design will facilitate improve the useful frequency of performance critical designs. Furthermore, the proposed design can be used as a typical scan flip-flop in the “mixed scan” take a look at wherein it will be used as a serial scan cell also a random access scan (RAS) cell. The mixed scan take a look at architecture has been implemented using the proposed scan flip-flop. The experimental results show a promising reduction in interconnect wire length, test time, and take a look at data volume, compared to the state-of-the-art RAS and multiple serial scan implementations.

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