PROJECT TITLE :
Low Power 1-Bit Full Adder Using Full-Swing Gate Diffusion Input Technique - 2018
This paper presents a design which provides full swing output for logic one and logic 0 for one-bit full adder cell and reduces power consumption, delay, and space. In this design full adder consists of two XOR gate cells and one cell of 2×one multiplexer (MUX). The performance of the proposed style compared with the different logic style for full adders through cadence virtuoso simulation based on TSMC 65nm technology models with a supply voltage of 1v and frequency 125MHz. The simulation results showed that the proposed full adder style dissipates low power, while improving delay and area among all the look taken for comparison.
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