Low Power 1-Bit Full Adder Using Full-Swing Gate Diffusion Input Technique - 2018 PROJECT TITLE :Low Power 1-Bit Full Adder Using Full-Swing Gate Diffusion Input Technique - 2018ABSTRACT:This paper presents a design which provides full swing output for logic one and logic 0 for one-bit full adder cell and reduces power consumption, delay, and space. In this design full adder consists of two XOR gate cells and one cell of 2×one multiplexer (MUX). The performance of the proposed style compared with the different logic style for full adders through cadence virtuoso simulation based on TSMC 65nm technology models with a supply voltage of 1v and frequency 125MHz. The simulation results showed that the proposed full adder style dissipates low power, while improving delay and area among all the look taken for comparison. Did you like this research project? To get this research project Guidelines, Training and Code... Click Here facebook twitter google+ linkedin stumble pinterest VLSI Backend MTech Projects Low Power 4×4 Bit Multiplier Design using Dadda Algorithm and Optimized Full Adder - 2018 A Low-Power Forward and Reverse Body Bias Generator in CMOS 40 nm - 2018
