PROJECT TITLE :
Improving Error Correction Codes for Multiple-Cell Upsets in Space Applications - 2018
Currently, faults suffered by SRAM memory systems have increased because of the aggressive CMOS integration density. Therefore, the chance of prevalence of single-cell upsets (SCUs) or multiple-cell upsets (MCUs) augments. One amongst the most causes of MCUs in house applications is cosmic radiation. A standard answer is the employment of error correction codes (ECCs). Nevertheless, when using ECCs in area applications, they have to achieve a smart balance between error coverage and redundancy, and their encoding/decoding circuits must be economical in terms of area, power, and delay. Totally different codes are proposed to tolerate MCUs. Parenthetically, Matrix codes use Hamming codes and parity checks in a bi-dimensional layout to correct and detect some patterns of MCUs. Recently presented, column–line–code (CLC) has been designed to tolerate MCUs in space applications. CLC could be a modified Matrix code, primarily based on extended Hamming codes and parity checks. Nevertheless, a standard property of these codes is the high redundancy introduced. In this paper, we tend to present a series of new low-redundant ECCs in a position to correct MCUs with reduced space, power, and delay overheads. Additionally, these new codes maintain, or maybe improve, memory error coverage with respect to Matrix and CLC codes.
Did you like this research project?
To get this research project Guidelines, Training and Code... Click Here