A Low-Power High-Speed Comparator for Precise Applications - 2018


A coffee-power comparator is presented. pMOS transistors are used at the input of the preamplifier of the comparator furthermore as the latch stage. Each stages are controlled by a special local clock generator. At the analysis part, the latch is activated with a delay to achieve enough preamplification gain and avoid excess power consumption. Meanwhile, little cross-coupled transistors increase the preamplifier gain and reduce the input common mode of the latch to strongly turn on the pMOS transistors (at the latch input) and scale back the delay. Unlike the traditional comparator, the proposed structure let us set the optimum delay for preamplification and avoid excess power consumption. The speed and the power benefits of the comparator were verified using solid analytical derivations, method–VDD–temperature corners, and Monte Carlo simulations along with silicon measurements in zero.18 µm . The tests make sure that the proposed circuit reduces the power consumption by fiftyp.c and provides thirtyp.c better comparison speed at the identical offset and almost the identical noise budgets. Moreover, the comparator provides a rail-to-rail input Vcm vary in fclk=500 MHz.

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