Efficient Design for Fixed-Width Adder-Tree - 2018


Conventionally, mounted-width adder-tree (AT) style is obtained from the total-width AT style by using direct or post-truncation. In direct-truncation, one lower order bit of each adder output of full-width AT is post-truncated, and in case of post-truncation, p lower order-bits of final-stage adder output are truncated, where p=log2N and N is the input-vector size. Both these ways does not give an efficient style. During this paper, a novel scheme is presented to obtain mounted-width AT design using truncated input. A bias estimation formula based on probabilistic approach is presented to compensate the truncation error. The proposed fixed-width AT style for input-vector sizes 8 and sixteen offers (thirty sevenp.c,23percent,twenty two%) and (fifty onep.c,30p.c,twenty seven%) space-delay product (ADP) saving for word-length sizes (eight,12,sixteen), respectively, and calculates the output nearly with the same accuracy as the post-truncated fastened-width AT that has the highest accuracy among the present fastened-width AT. Additional, we have a tendency to observed that Walsh-Hadamard remodel based mostly on the proposed fixed-width AT style reconstruct higher-texture pictures with higher peak signal to noise ratio (PSNR) and moderate-texture pictures with nearly the same PSNR compared to those obtained using the existing AT designs. Besides, the proposed style creates an additional advantage to optimize different blocks seem at the upstream of the AT during a complex style.

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