High Performance Integer DCT Architectures For HEVC - 2017


This paper proposes an efficient VLSI design for integer discrete cosine remodel (integer DCT) that is utilized in real time high potency video coding (HEVC) applications. The proposed N-point 1D-Integer DCT architecture consists of signed configurable carry save adder tree based multiplier unit. So, the depth of the architecture falls among the bounds of O(log2 N). The proposed 1D architecture is employed to perform one N-purpose or multiple N a pair of ; N four ; :::two-purpose Integer DCTs in parallel. The proposed 1D architecture is used to design 2D folded and parallel styles. The performance results show that the proposed design provides better performance compared with existing architectures using 45 nm CMOS TSMC library. The proposed 32thirty two-purpose parallel Integer DCT achieves 59:1percent of improvement in worst path delay compared with odd-even decomposition [3] based mostly design.

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