Logic BIST with Capture-per-Clock Hybrid Test Points - 2018

PROJECT TITLE :

Logic BIST with Capture-per-Clock Hybrid Test Points - 2018

ABSTRACT:

Logic engineered-in self-check (LBIST) is now increasingly used with on-chip check compression as a complementary answer for in-system check, where prime quality, low power, low silicon space, and most importantly short take a look at application time are key factors affecting ICs targeted for safety-crucial systems. Test points, common in LBIST-prepared designs, will help to scale back test time and the silicon overhead therefore that one will get desired check coverage with the minimal number of patterns. Sometimes, LBIST check points are dysfunctional when enabled in an ATPG-based take a look at compression mode. Similarly, check points used to cut back ATPG pattern counts cannot guarantee desired random testability. In this paper, we have a tendency to present a hybrid test purpose technology designed to reduce deterministic pattern counts and to improve fault detection probability by means that of the same minimal set of test points. The hybrid test points are subsequently deployed during a scan-based LBIST scheme addressing stringent take a look at necessities of bound application domains like the automotive electronics market. These requirements, largely driven by safety standards, are met by significantly reducing test application time while preserving the high fault coverage. The new theme could be a combination of pseudorandom check patterns delivered in a very test-per-clock fashion through conventional scan chains and per-cycle-driven hybrid observation take a look at points that capture faulty effects each shift cycle into dedicated scan chains. Their content is gradually shifted into a compactor shared with the remaining chains that deliver responses once a take a look at pattern has been shifted-in. Experimental results obtained for industrial designs ensure feasibility of the new schemes, and they are reported herein.

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