Optimizing Power-Accuracy trade-off in Approximate Adders - 2018


Approximate circuit design has gained significance in recent years targeting applications like media processing where full accuracy isn't required. During this paper, we propose an approximate adder in that the approximate half of the total is obtained by finding a single optimal level that minimises the mean error distance. Therefore hardware required for the approximate part computation can be removed, which effectively ends up in terribly low power consumption. We tend to compare the proposed adder with numerous approximate adders within the literature in terms of power and accuracy metrics. The power savings of our adder is shown to be 17percent to 55p.c a lot of than power savings of the present approximate adders over a significant vary of accuracy values. More, in a picture addition application, this adder is shown to produce the most effective trade-off between PSNR and power.

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