Design and simulation of CRC encoder and decoder using VHDL - 2018


Cyclic Redundancy Check (CRC) technique is an efficient error detection technique that used to detect single and burst errors. CRC technique adds redundancy bits to the first dat. The redundancy bits represent the remainder of division between the original message and the chosen polynomial. At the receiver side, the received data can be recognized as valid or not. In this paper, an economical CRC (eight) encoder and decoder circuits are designed and implemented using VHDL. Xilinx ISE Simulator is employed for circuits verification and validation for CRC (eight) (Cyclic Redundancy Checking with an input 8-bit polynomial), five and eight-bit input knowledge. The results reveal that the proposed circuits are efficient in terms of hardware utilization rate.

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