PROJECT TITLE :
Design of Area-Efficient and Highly Reliable RHBD 10T Memory Cell for Aerospace Applications - 2018
In this brief, based on upset physical mechanism along with cheap transistor size, a sturdy 10T memory cell is first proposed to enhance the reliability level in aerospace radiation setting, while keeping the main benefits of tiny area, low power, and high stability. Using Taiwan Semiconductor Manufacturing Company sixty five-nm CMOS commercial commonplace method, simulations performed in Cadence Spectre demonstrate the ability of the proposed radiation-hardened-by-design 10T cell to tolerate both 0 ? 1 and one ? 0 single node upsets, with the increased browse/write access time.
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