PROJECT TITLE :
Architecture Generator for Type-3 Unum Posit Adder/Subtractor - 2018
This paper is aimed towards the hardware architecture aspect of a recently proposed posit range system under kind-three unum (universal variety system). Here, an algorithmic flow for the posit addition/subtraction arithmetic is developed and its hardware architecture is intended. Compare to floating purpose, posit provides better dynamic vary and accuracy over same word size, together with additional accurate and exact arithmetic support. Posit format includes a run-time varying exponent component, provided by a combination of regime-bits (of run-time varying length) and exponent-bits (of size up to ES bits). Thus, the mantissa precision conjointly varies at run-time. This provides a mixture of dynamic vary and precision beneath a given word size (N). This potential variation in format along dynamic range and precision might attract numerous applications with different(accuracy and dynamic vary) requirement. But, this run-time variation in posit format conjointly poses a hardware design challenge. Therefore, this paper is aimed towards the construction of an open-supply parameterized Verilog HDL (Hardware Description Language) generator for posit adder/subtractor arithmetic, with parameterized N and ES.
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