A Low-Power Configurable Adder for Approximate Applications - 2018 PROJECT TITLE :A Low-Power Configurable Adder for Approximate Applications - 2018ABSTRACT:Addition is a key fundamental perform for several error-tolerant applications. Approximate addition is taken into account to be an economical technique for trading off energy against performance and accuracy. This paper proposes a carry-maskable adder whose accuracy can be configured at runtime. The proposed scheme can dynamically select the length of the carry propagation to satisfy the quality requirements flexibly. Compared with a standard ripple carry adder and a typical carry look-ahead adder, the proposed sixteen-bit adder reduced power consumption by 54.1p.c and 57.5percent and vital path delay by seventy two.5% and 54.twop.c, respectively. In addition, results from a picture processing application indicate that the standard of the processed images will be controlled by the proposed adder. Did you like this research project? To get this research project Guidelines, Training and Code... Click Here facebook twitter google+ linkedin stumble pinterest VLSI Core MTech Projects A Low-Power High-Speed Accuracy-Controllable Approximate Multiplier Design - 2018 Approximate Quaternary Addition with the Fast Carry Chains of FPGAs - 2018
