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List of articles in category MTech VLSI Projects
No. Project Titles Abstract
201. Improved 64-bit Radix-16 Booth Multiplier Based on Partial Product Array Height Reduction - 2017 Abstract
202. High-Speed and Low-Power VLSI-Architecture for Inexact Speculative Adder - 2017 Abstract
203. Energy-Efficient Approximate Multiplier Design usingBit Significance-Driven Logic Compression - 2017 Abstract
204. Design and Analysis of Multiplier Using Approximate 15-4 Compressor - 2017 Abstract
205. Sign-Magnitude Encoding for Efficient VLSI Realization of Decimal Multiplication - 2017 Abstract
206. Majority-Logic-Optimized Parallel Prefix Carry Look-Ahead Adder Families Using Adiabatic Quantum-Flux-Parametron Logic - 2017 Abstract
207. Energy-Efficient VLSI Realization of Binary64 Division With Redundant Number Systems - 2017 Abstract
208. DSP48E Efficient Floating Point Multiplier Architectures on FPGA - 2017 Abstract
209. Fast Energy Efficient Radix-16 Sequential Multiplier - 2017 Abstract
210. A Residue-to-Binary Converter for the Extended Four-Moduli Set {2n− 1, 2n+ 1, 22n+ 1, 22n+p} - 2017 Abstract
211. Majority Logic Formulations for Parallel Adder Designs at Reduced Delay and Circuit Complexity - 2017 Abstract
212. Design And Synthesis Of Combinational Circuits Using Reversible Decoder In Xilinx - 2017 Abstract
213. Design of Approximate Radix-4 Booth Multipliers for Error-Tolerant Computing - 2017 Abstract
214. Design of Power and Area Efficient Approximate Multipliersc - 2017 Abstract
215. Dual-Quality 4:2 Compressors for Utilizing in Dynamic Accuracy Configurable Multipliers - 2017 Abstract
216. A Slack-based Approach to Efficiently Deploy Radix 8 Booth Multipliers - 2017 Abstract
217. A Low Error Energy-Efficient Fixed-Width Booth Multiplier with Sign-Digit-Based Conditional Probability Estimation - 2017 Abstract
218. High Performance Parallel Decimal Multipliers Using Hybrid BCD Codes - 2017 Abstract
219. An Improved Design of a Reversible Fault Tolerant LUT-Based FPGA - 2016 Abstract
220. A Fixed-Point Squaring Algorithm Using an Implicit Arbitrary Radix Number System - 2016 Abstract
221. An Improved Signed Digit Representation Approach for Constant Vector Multiplication - 2016 Abstract
222. Area-Delay Efficient Digit-Serial Multiplier Based on kPartitioning Scheme Combined With TMVP Block Recombination Approach - 2016 Abstract
223. Area-Delay-Power-Aware Adder Placement Method for RNS Reverse Converter Design - 2016 Abstract
224. Efficient Implementation of Scan Register Insertion on Integer Arithmetic Cores for FPGAs - 2016 Abstract
225. Logic Synthesis in Reversible PLA - 2016 Abstract
226. MAC Unit for Reconfigurable Systems Using Multi- Operand Adders with Double Carry-Save Encoding - 2016 Abstract
227. Multi Precision Arithmetic Adders - 2016 Abstract
228. Weighted Partitioning for Fast Multiplier-less Multiple Constant Convolution Circuit - 2016 Abstract
229. Low complexity and area efficient reconfigurable multimode inter leaver address generator for multi standard radios - 2016 Abstract
230. High-Speed and Energy-Efficient Carry Skip Adder Operating Under a Wide Range of Supply Voltage Levels - 2016 Abstract
231. Efficient implementation of bit-parallel fault tolerant polynomial basis multiplication and squaring over GF(2m) - 2016 Abstract
232. Measuring Improvement When Using HUB Formats to Implement Floating-Point Systems Under Round-to-Nearest - 2016 Abstract
233. Flexible DSP Accelerator Architecture Exploiting Carry-Save Arithmetic - 2016 Abstract
234. A Modified Partial Product Generator for Redundant Binary Multipliers - 2016 Abstract
235. Pre-Encoded Multipliers Based on Non-Redundant Radix-4 Signed-Digit Encoding - 2016 Abstract
236. Arithmetic algorithms for extended precisionusing floating-point expansions - 2016 Abstract
237. Performance/Power Space Exploration for Binary64 Division Units - 2016 Abstract
238. On Efficient Retiming of Fixed-Point Circuits - 2016 Abstract
239. Hybrid LUT/Multiplexer FPGA Logic Architectures - 2016 Abstract
240. VLSI Design for Convolutive BlindSource Separation - 2016 Abstract
241. Concept, Design, and Implementation of Reconfigurable CORDIC - 2016 Abstract
242. Ultralow-Energy Variation-Aware Design: Adder Architecture Study - 2016 Abstract
243. Floating-Point Butterfly Architecture Based on Binary SignedDigit Representation - 2016 Abstract
244. Design and Implementation of Area-Efficient and Low-Power Configurable Booth-Multiplier - 2016 Abstract
245. Design and Analysis of Inexact Floating-Point Adders - 2016 Abstract
246. Low-Cost High-Performance VLSI Architecture forMontgomery Modular Multiplication - 2016 Abstract
247. High speed hybrid double multiplication architectures using new serial out bit level mastrovito multiplier - 2016 Abstract
248. A 520k (18 900, 17 010) Array Dispersion LDPC Decoder Architectures for NAND-Flash Memory - 2016 Abstract
249. Input-Based Dynamic Reconfiguration of Approximate Arithmetic Units for Video Encoding - 2016 Abstract
250. Implementing Minimum-Energy-Point Systems With Adaptive Logic - 2016 Abstract
251. Algorithm and Architecture of Configurable Joint Detection and Decoding for MIMO Wireless Communications With Convolution Codes - 2016 Abstract
252. High-Performance NB-LDPC Decoder With Reduction of Message Exchange - 2016 Abstract
253. Exploiting Intracell Bit-Error Characteristics to Improve Min-Sum LDPC Decoding for MLC NAND Flash-Based Storage in Mobile Device - 2016 Abstract
254. Unequal-Error-Protection Error Correction Codes for the Embedded Memories in Digital Signal Processors - 2016 Abstract
255. Design and FPGA Implementation of a Reconfigurable 1024-Channel Channelization Architecture for SDR Application - 2016 Abstract
256. Low-Power/Cost RNS Comparison via Partitioning the Dynamic Range - 2016 Abstract
257. Understanding the Relation Between the Performance and Reliability of NAND Flash/SCM Hybrid Solid-State Drive - 2016 Abstract
258. Optimized Built-In Self-Repair for Multiple Memories - 2016 Abstract
259. A High-Throughput Hardware Design of a One-Dimensional SPIHT Algorithm - 2016 Abstract
260. Network-on-Chip for Turbo Decoders - 2016 Abstract
261. Enhanced Wear-Rate Leveling for PRAM Lifetime Improvement Considering Process Variation - 2016 Abstract
262. Speculative Look ahead for Energy-Efficient Microprocessors - 2016 Abstract
263. Efficient Synchronization for Distributed Embedded Multiprocessors - 2016 Abstract
264. NAND Flash Memory With Multiple Page Sizes for High-Performance Storage Devices - 2016 Abstract
265. A Performance Degradation Tolerable Cache Design by Exploiting Memory Hierarchies - 2016 Abstract
266. Knowledge-Based Neural Network Model for FPGA Logical Architecture Development - 2016 Abstract
267. A New Optimal Algorithm for Energy Saving in Embedded System With Multiple Sleep Modes - 2016 Abstract
268. A Fast Fault-Tolerant Architecture for Sauvola Local Image Thresholding Algorithm Using Stochastic Computing - 2016 Abstract
269. Write Buffer-Oriented Energy Reduction in the L1 Data Cache for Embedded Systems - 2016 Abstract
270. Toward Solving Multichannel RF-SoC Integration Issues Through Digital Fractional Division - 2016 Abstract
271. Error Resilient and Energy Efficient MRF Message-Passing-Based Stereo Matching - 2016 Abstract
272. Trigger-Centric Loop Mapping on CGRAs - 2016 Abstract
273. Area-Aware Cache Update Trackers for Post silicon Validation - 2016 Abstract
274. PEVA: A Page Endurance Variance Aware Strategy for the Lifetime Extension of NAND Flash - 2016 Abstract
275. Memory-Aware Loop Mapping on Coarse-Grained Reconfigurable Architectures - 2016 Abstract
276. A High-Throughput Energy-Efficient Implementation of Successive Cancellation Decoder for Polar Codes Using Combinational Logic - 2016 Abstract
277. An Efficient Decoder Architecture for Non-binary LDPC Codes with Extended Min-Sum Algorithm - 2016 Abstract
278. An Efficient Eligible Error Locator Polynomial Searching Algorithm and Hardware Architecture for One-Pass Chase BCH Codes Decoding - 2016 Abstract
279. An Efficient Implementation of a Fully Combinational Pipelined S-Box on FPGA - 2016 Abstract
280. CWFP: Novel Collective Write back and Fill Policy for LastLevel DRAM Cache - 2016 Abstract
281. High Performance Reconfigurable Viterbi Decoder Design for Multi-Standard Receiver - 2016 Abstract
282. Reducing the Cost of Triple Adjacent Error Correction in Double Error Correction Orthogonal Latin Square Codes - 2016 Abstract
283. A Multimode Area-Efficient SCL Polar Decoder - 2016 Abstract
284. Optimizing the Implementation of SEC–DAEC Codes in FPGAs - 2016 Abstract
285. A Cache-Assisted Scratchpad Memory for Multiple-Bit-Error Correction - 2016 Abstract
286. High-Performance Pipelined Architecture of Elliptic Curve Scalar Multiplication Over GF(2m) - 2016 Abstract
287. A High Throughput List Decoder Architecturefor Polar Codes - 2016 Abstract
288. Fault Tolerant Parallel FFTs Using Error Correction Codes and Parseval Checks - 2016 Abstract
289. A New XOR-Free Approach for Implementation of Convolutional Encoder - 2016 Abstract
290. A New CDMA Encoding/Decoding Method for on-Chip Communication Network - 2016 Abstract
291. An Efficient Single and Double-Adjacent Error Correcting Parallel Decoder for the (24,12) Extended Golay Code - 2016 Abstract
292. High-Performance Deadlock-Free ID Assignment for Advanced Interconnect Protocols - 2016 Abstract
293. Digital Multiplierless Realization of Two-CoupledBiological Hindmarsh–Rose Neuron Model - 2016 Abstract
294. Low-Cost Multiple Bit Upset Correction in SRAM-Based FPGA Configuration Frames - 2016 Abstract
295. A Method to Design Single Error Correction Codes With Fast Decoding for a Subset of Critical Bits - 2016 Abstract
296. Hardware and Energy-Efficient Stochastic LU Decomposition Scheme for MIMO Receivers - 2016 Abstract
297. Memory-Reduced Turbo Decoding ArchitectureUsing NII Metric Compression - 2016 Abstract
298. In-Field Test for Permanent Faults in FIFO Buffers of NoC Routers - 2016 Abstract
299. A Cellular Network Architecture WithPolynomial Weight Functions - 2016 Abstract
300. A Novel Coding Scheme for Secure Communications in Distributed RFID Systems - 2016 Abstract

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