PROJECT TITLE :
A Low-Power Yet High-Speed Configurable Adder for Approximate Computing - 2018
Approximate computing is an efficient approach for error-tolerant applications as a result of it will trade off accuracy for power. Addition is a key basic perform for these applications. In this paper, we have a tendency to proposed an occasional-power yet high-speed accuracy-configurable adder that additionally maintains a little design space. The proposed adder relies on the traditional carry look-ahead adder, and its configurability of accuracy is realized by masking the carry propagation at runtime. Compared with the conventional carry look-ahead adder, with solely 14.fivepercent space overhead, the proposed sixteen-bit adder reduced power consumption by 42.7percent, and vital path delay by fifty six.9p.c most according to the accuracy configuration settings, respectively. Furthermore, compared with alternative previously studied adders, the experimental results demonstrate that the proposed adder achieved the original purpose of optimizing both power and speed simultaneously without reducing the accuracy.
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