Parallel Pseudo-Exhaustive Testing of Array Multipliers with Data-Controlled Segmentation - 2018 PROJECT TITLE :Parallel Pseudo-Exhaustive Testing of Array Multipliers with Data-Controlled Segmentation - 2018ABSTRACT:This paper presents a brand new method for pseudo-exhaustive testing of standard array multipliers employing a novel approach of data-controlled segmentation of the circuit. The method covers both combinational and sequential fault classes. Differently from previous papers, the proposed separate cell-testing approach targets multiple faults in several cells and avoids fault masking. The strategy is additionally applicable to other multiplier architectures like Booth and MiniMIPS with high stuck-at fault (SAF) coverage. The regular structure of the test allows economical implementation of the method as each software primarily based self-check (SBST) and hardware-based BIST. Did you like this research project? To get this research project Guidelines, Training and Code... Click Here facebook twitter google+ linkedin stumble pinterest VLSI Testing MTech Projects Improving Error Correction Codes for Multiple-Cell Upsets in Space Applications - 2018 Logic BIST with Capture-per-Clock Hybrid Test Points - 2018
