PROJECT TITLE :
VLSI design of low-cost and high-precision fixed-point reconfigurable FFT processors - 2018
Quick Fourier transform (FFT) plays an vital role in digital signal processing systems. In this study, the authors explore the terribly large-scale integration (VLSI) style of high-precision mounted-point reconfigurable FFT processor. To realize high accuracy under the restricted wordlength, this study analyses the quantisation noise in FFT computation and proposes the mixed use of multiple scaling approaches to compensate the noise. Yet, a statistics-primarily based optimisation scheme is proposed to configure the scaling operations of the cascaded arithmetic blocks at each stage for yielding the foremost optimised accuracy for a given FFT length. On the basis of this approach, they additional present a VLSI implementation of space-efficient and high-precision FFT processor, which can perform power-of-2 FFT from 32 to 8192 points. By using the SMIC zero.thirteen µm process, the world of the proposed FFT processor is 27 mm 2 with a maximum operating frequency of four hundred MHz. When the FFT processor is configured to perform 8192-point FFT at forty MHz, the signal-to-quantisation-noise ratio is up to 53.28 dB and the facility consumption measured by post-layout simulation is thirty five.seven mW.
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