PROJECT TITLE :
A 16-mW 1-GS/s with 49.6-dB SNDR TI-SAR ADC for Software-Defined Radio in 65-nm CMOS - 2018
This paper presents a ten-bit one-GS/s four-channel time-interleaved (TI) successive approximation register (SAR) analog-to-digital converter (ADC). To suppress the time skew, the complete rate master clock-primarily based sampling technique is adopted. The effect of sampling switch mismatches on time skew is addressed. The measured time skew spurs caused by the sampling switch mismatches are around -fifty two to -55 dB at Nyquist input. Then, a faucet-interpolating fractional delay filters-based digital background time skew calibration technique is proposed. Additionally, a full analysis of the effects of the numerous parameters on the time skew generated spur levels is presented, that indicates that the time skew error level is connected to the length of calibration filters, calibration vary, and bandwidth penalty. The subchannel ADC exploits a 250-MS/s SAR ADC with a coffee-price high-speed subradix-a pair of searching technique. The reference interference of nonbinary TI ADCs is mentioned and tolerated by the subradix-2 searching scheme. The proposed adders-primarily based encoding circuit is optimized with lower propagation delay to satisfy high-speed requirements. The prototype was fabricated in a very sixty five-nm CMOS technology. The measurement results show that the ADC achieves a symptom-to-noise-and-distortion ratio of forty nine.vi dB with a power of 15.ninety five mW and a figure of advantage of sixty three fJ/conversion step when operating at one-GS/s and 458.one-MHz Nyquist input. The ADC core achieves an area of zero.158 mm2.
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