Efficient Fixed/Floating-Point Merged Mixed-Precision Multiply-Accumulate Unit for Deep Learning Processors - 2018


Deep learning is getting additional and more attentions in recent years. Many hardware architectures have been proposed for economical implementation of deep neural network. The arithmetic unit, as a core processing half of the hardware design, can confirm the functionality of the entire design. During this paper, an economical fastened/floating-point merged multiply-accumulate unit for deep learning processor is proposed. The proposed architecture supports 16-bit 0.5-precision floating-point multiplication with 32-bit single-precision accumulation for training operations of deep learning algorithm. Similarly, among the identical hardware, the proposed design also supports 2 parallel 8-bit fastened-point multiplications and accumulating the product to 32-bit fixed-purpose variety. This will enable higher throughput for inference operations of deep learning algorithms. Compared to a 0.5-precision multiply-accumulate unit (accumulating to single-precision), the proposed design has only four.6percent space overhead. With the proposed multiply-accumulate unit, the deep learning processor can support both coaching and high-throughput inference.

Did you like this research project?

To get this research project Guidelines, Training and Code... Click Here

PROJECT TITLE :Efficient Secure Outsourcing of Large-Scale Sparse Linear Systems of Equations - 2018ABSTRACT:Solving large-scale sparse linear systems of equations (SLSEs) is one in all the foremost common and basic problems in
PROJECT TITLE :Distributed Feature Selection for Efficient Economic Big Data Analysis - 2018ABSTRACT:With the rapidly increasing popularity of economic activities, a large amount of economic data is being collected. Although
PROJECT TITLE :Efficient Wideband DOA Estimation Through Function Evaluation Techniques - 2018ABSTRACT:This Project presents an economical analysis methodology for the functions involved within the computation of direction-of-arrival
PROJECT TITLE :Efficient System Tracking With Decomposable Graph-Structured Inputs and Application to Adaptive Equalization With Cyclostationary Inputs - 2018ABSTRACT:This Project introduces the graph-structured recursive least
PROJECT TITLE :Efficient Partial-Sum Network Architectures for List Successive-Cancellation Decoding of Polar Codes - 2018ABSTRACT:List successive cancellation decoder (LSCD) architectures have been recently proposed for the decoding

Ready to Complete Your Academic MTech Project Work In Affordable Price ?

Project Enquiry