Systematic Design of an Approximate Adder: The Optimized Lower Part Constant-OR Adder - 2018 PROJECT TITLE :Systematic Design of an Approximate Adder: The Optimized Lower Part Constant-OR Adder - 2018ABSTRACT:Exploiting the tradeoff between accuracy and hardware cost incorporates a tremendous potential to boost the efficiency of integrated systems. Using this concept, various approximate adders have been proposed in the last 10 years. Although conceptually totally different, all previous architectures have been obtained with an unplanned and nonsystematic methodology. Instead, this temporary generalizes and systematically optimizes an architectural template for approximate adders. The outcome, referred to as optimized lower half constant-OR adder (LOCA), outperforms previous approaches in terms of accuracy and hardware value. For example, an eight-bit approximate adder implemented with our new approach improves the mean squared error by 58.5p.c, while simultaneously reducing the value by 7.2% with respect to the previously reported best design. Did you like this research project? To get this research project Guidelines, Training and Code... Click Here facebook twitter google+ linkedin stumble pinterest VLSI Core MTech Projects Towards Efficient Modular Adders based on Reversible Circuits - 2018 Reducing the Hardware Complexity of a Parallel Prefix Adder - 2018
