Efficient Implementations of 4-Bit Burst Error Correction for Memories - 2018


In recent times, there has been a growing interest in error correction codes that can correct localized errors in reminiscences. This is due to the larger fraction of radiation induced error events that affect many nearby memory cells as technology scales. Initially, codes which will correct single and double adjacent errors were proposed. More recently, three-bit burst error correction codes have additionally been presented. Consecutive step is to produce efficient 4-bit burst error correction for reminiscences. The issue is that because the error correction capability increases so does the overheads required to implement the codes in terms of parity check bits and encoding and decoding complexity. In this paper, efficient solutions to safeguard reminiscences against four-bit bursts are presented. The first one is the use of two interleaved single and double adjacent error correction codes whereas in the second, economical 4-bit burst error correction codes are presented. The primary resolution reduces the decoding complexity and delay at the value of having additional parity check bits whereas the second tries to reduce the decoding complexity when using the minimum variety of parity check bits. Each solutions have been evaluated and compared to an interleaved single error correction code and with existing burst error correction codes to raised understand the overheads needed to attain the protection against 4-bit burst errors.

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