Low-Power Noise-Immune Nano scale Circuit Design Using Coding-Based Partial MRF Method - 2018 PROJECT TITLE :Low-Power Noise-Immune Nano scale Circuit Design Using Coding-Based Partial MRF Method - 2018ABSTRACT:Reliability is one amongst the major concerns for ultralow power circuit designs. Markov random field (MRF) techniques are applied to logic circuits to resist random noise when operating below ultralow supply voltage or sub-threshold voltage. Although conventional MRF networks will be simply mapped onto straightforward logic circuits, it becomes troublesome when the circuits are giant and complex. During this paper, we tend to present a general coding-primarily based partial MRF (CPMRF) methodology for multi-logic operations in one basic unit, which is known as a CPMRF pair. A CPMRF try saves circuit space by sharing a standard MRF network. It also inherits noise immunity from the MRF theory whereas obtaining noise immunity from the coding structure as a mixture of strong “1s” and “0s.” The resulting architectures become a lot of price effective than standard ones. To validate the performance of our proof-of-concept design, we tend to fabricated a carry-lookahead adder implemented by the proposed CPMRF pairs using IBM a hundred thirty-nm CMOS technology. Measurement results indicate that the CPMRF CLA can achieve high noise tolerance with 20p.c improvement while occupying thirty seven.seven% less space and reducing power consumption by 93p.c compared with the master-and-slave MRF CLA design. Did you like this research project? To get this research project Guidelines, Training and Code... Click Here facebook twitter google+ linkedin stumble pinterest VLSI Communication MTech Projects Reconfigurable Decoder for LDPC and Polar Codes - 2018 An Efficient VLSI Architecture for Convolution Based DWT Using MAC - 2018
