Low-Power Noise-Immune Nano scale Circuit Design Using Coding-Based Partial MRF Method - 2018


Reliability is one amongst the major concerns for ultralow power circuit designs. Markov random field (MRF) techniques are applied to logic circuits to resist random noise when operating below ultralow supply voltage or sub-threshold voltage. Although conventional MRF networks will be simply mapped onto straightforward logic circuits, it becomes troublesome when the circuits are giant and complex. During this paper, we tend to present a general coding-primarily based partial MRF (CPMRF) methodology for multi-logic operations in one basic unit, which is known as a CPMRF pair. A CPMRF try saves circuit space by sharing a standard MRF network. It also inherits noise immunity from the MRF theory whereas obtaining noise immunity from the coding structure as a mixture of strong “1s” and “0s.” The resulting architectures become a lot of price effective than standard ones. To validate the performance of our proof-of-concept design, we tend to fabricated a carry-lookahead adder implemented by the proposed CPMRF pairs using IBM a hundred thirty-nm CMOS technology. Measurement results indicate that the CPMRF CLA can achieve high noise tolerance with 20p.c improvement while occupying thirty less space and reducing power consumption by 93p.c compared with the master-and-slave MRF CLA design.

Did you like this research project?

To get this research project Guidelines, Training and Code... Click Here

PROJECT TITLE : Low-Power Wide-Area Networks: A Broad Overview of Its Different Aspects ABSTRACT: Low-power wide-area networks, also known as LPWANs, are becoming increasingly popular in the field of research due to the fact
PROJECT TITLE :Design, Analysis, and Implementation of ARPKI: An Attack-Resilient Public-Key Infrastructure - 2018ABSTRACT:This Transport Layer Security (TLS) Public-Key Infrastructure (PKI) is based on a weakest-link security
PROJECT TITLE :Dynamically Updatable Ternary Segmented Aging Bloom Filter for OpenFlow-Compliant Low-Power Packet Processing - 2018ABSTRACT:OpenFlow, the most protocol for software-outlined networking, requires large-sized rule
PROJECT TITLE :A Low-Power High-Speed Comparator for Precise Applications - 2018ABSTRACT:A coffee-power comparator is presented. pMOS transistors are used at the input of the preamplifier of the comparator furthermore as the latch
PROJECT TITLE :Low-power Implementation of Mitchell's Approximate Logarithmic Multiplication for Convolutional Neural Networks - 2018ABSTRACT:This paper proposes an occasional-power implementation of the approximate logarithmic

Ready to Complete Your Academic MTech Project Work In Affordable Price ?

Project Enquiry