PROJECT TITLE :
Tap Delay-and-Accumulate Cost Aware Coefficient Synthesis Algorithm for the Design of Area-Power Efficient FIR Filters - 2018
Finite-impulse response filters are widely used in Digital Signal Processing applications. Prodigious analysis in the past 2 decades has substantially reduced the implementation price of the multiple constant multiplication blocks. Any area and power consumption savings are stagnated by the structural adders and registers in the tap delay-and-accumulate line, that sadly dominate the hardware value of FIR filter and are troublesome to reduce by existing resource sharing approaches. Retiming or relocating the structural adders and registers will improve merely the throughput. To shut the area-power potency gap, we tend to reformulate the filter coefficient synthesis problem to explore the look area for the tap delay-and accumulate line by bisecting at some tap position. An economical Genetic Algorithm is proposed to unravel this integer programming problem at quadratic computational complexity by refining the search space for finding an optimized resolution to meet the frequency response specifications. Field programmable gate array and application specific integrated circuit logic synthesis results from twelve benchmark filter specifications showed that the typical area and power consumptions of the solutions generated by our proposed algorithm are reduced by up to twenty six.8% and twenty seven.5% respectively, in comparison with the solutions obtained by existing style ways.
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