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S.No Project Titles Abstract
1 A CMOS PWM Transceiver Using Self-Referenced Edge Detection - 2015 Abstract
2 Efficient Static D-Latch Standard Cell Characterization Using a Novel Setup Time Model - 2015 Abstract
3 High-Frequency CMOS Active Inductor Design Methodology and Noise Analysis - 2015 Abstract
4 High-Performance and High-Yield 5 nm Underlapped FinFET SRAM Design using P-type Access Transistors - 2015 Abstract
5 On the Nonvolatile Performance of Flip-FlopSRAM Cells With a Single MTJ - 2015 Abstract
6 Read Performance The Newest Barrier in Scaled STT-RAM - 2015 Abstract
7 An All-Digital Scalable and Reconfigurable Wide-Input Range Stochastic ADC Using Only Standard Cells - 2015 Abstract
8 A Sub-mW, Ultra-Low-Voltage, Wideband Low-Noise Amplifier Design Technique - 2015 Abstract
9 A Highly-Scalable Analog Equalizer Using a Tunable and Current-Reusable Active Inductor for 10-Gb/s I/O Links - 2015 Abstract
10 A High Speed 256-Bit Carry Look Ahead Adder Design Using 22nm Strained Silicon Technology - 2015 Abstract
11 A 0.325 V, 600-kHz, 40-nm 72-kb 9T Subthreshold SRAM with Aligned Boosted Write Wordline and Negative Write Bitline Write-Assist - 2015 Abstract
12 A 0.25-V 28-nW 58-dB Dynamic Range Asynchronous Delta Sigma Modulator in 130-nm Digital CMOS Process - 2015 Abstract
13 Design and Performance Evaluation of A Low Transistor Ternary CNTFET SRAM Cell - 2015 Abstract
14 Design and simulation of single layered Logic Generator Block using Quantum Dot Cellular Automata - 2015 Abstract
15 Design of high speed ternary full adder and threeinput XOR circuits using CNTFETs - 2015 Abstract
16 Digtial to time converter using SET - 2015 Abstract
17 Low Power Multiplier Architectures Using Vedic Mathematics in 45nm Technology for High Speed Computing - 2015 Abstract
18 Low-power, high-speed dual modulus prescalers based on branch-merged true single-phase clocked scheme - 2015 Abstract
19 Voltage mode implementation of highly accurate analog multiplier circuit - 2015 Abstract
20 TM-RF Aging-Aware Power-Efficient Register File Design for Modern Microprocessors - 2015 Abstract
21 Frequency-Tuning Negative-Conductance Boosted Structure and Applications for Low-Voltage Low-Power Wide-Tuning-Range VCO - 2015 Abstract
22 A Sub-mW, Ultra-Low-Voltage, Wideband Low-Noise Amplifier Design Technique - 2015 Abstract
23 Design and synthesis of bandwidth efficient QPSK modulator for low power VLSI design - 2015 Abstract
24 Low-Power Programmable PRPG With Test Compression Capabilities - 2015 Abstract
25 Power Optimization of Communication System Using Clock Gating Technique - 2015 Abstract

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Disclaimer : MTech Projects, is not associated or affiliated with IEEE, in any way. The mentioned IEEE Projects here are student projects inspired by ideas from IEEE publications, not projects conducted by or associated with IEEE.

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