A Sub-mW, Ultra-Low-Voltage, Wideband Low-Noise Amplifier Design Technique - 2015
This project presents a design methodology for an ultra-low-power (ULP) and ultra-low-voltage (ULV) ultra-wideband (UWB) resistive-shunt feedback low-noise amplifier (LNA). The ULV circuit design challenges are discussed and a brand new biasing metric for ULV and ULP styles in deep-submicrometer CMOS technologies is introduced. Series inductive peaking within the feedback loop is analyzed and utilized to boost the bandwidth and noise performance of the LNA. Exploiting the new biasing metric, the planning methodology, and series inductive peaking in the feedback loop, a zero.five V, 0.75-mW broadband LNA with a current reuse scheme is implemented in a very ninety-nm CMOS technology. Measurement results show 12.half dozen-dB voltage gain, zero.1-7-GHz bandwidth, 5.5-dB NF, -nine-dBm IIP3, and -18-dB P1dB whereas occupying 0.23 mm2.
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